集成电路可靠性设计，专注于静电放电(ESD)与闩锁(Latch-up)保护研究

集成电路EDA技术研究，专注于高速射频器件与电路智能综合

代表性论文：

1. Guangyi Lu*, Lihui Wang, Ling Wang, Xin Gao, Jiahao Wei and Haiming Wang, “Troubleshooting a High-Leakage Issue of an Overdrive FinFET ESD Power Clamp From Fabrication Perspective,” IEEE Trans. Electron Devices, vol. 72, no. 1, pp. 62-67, Jan. 2025.

2. Jiahao Wei, Weiqi Chen, Qi Wu, Guangyi Lu*, Wei Gao, Lihui Wang, Mei Li and Haiming Wang*, “Microwave Network-Assisted Analysis and Machine Learning-Assisted Synthesis of Arbitrarily Tapped Coils and Its Application to On-Chip Ultrawideband ESD Protection Circuits,” IEEE Trans. Comput-Aided Des. Integr. Circuits Syst., vol. 43, no. 12, pp. 4386–4397, Dec. 2024.

3. Guangyi Lu*, Lihui Wang, Ling Wang, Xin Gao and Mei Li, “Investigation on Fabrication-induced High-leakage Issue of an Overdrive ESD Power Clamp in Advanced FinFET Technology,” in Proc. IEDS, 2021, pp. 1-5.

4. Guangyi Lu, Yuan Wang*, Yize Wang and Xing Zhang*, “Low-leakage ESD power clamp design with adjustable triggering voltage for nanoscale applications,” IEEE Trans. Electron Devices, vol. 64, no. 9, pp. 3569-3575, Sep. 2017.

5. Guangyi Lu, Yuan Wang* and Xing Zhang, “Transient and static hybrid-triggered active clamp design for power-rail ESD protection,” IEEE Trans. Electron Devices, vol. 63, no. 12, pp. 4654-4660, Dec. 2016.

6. Guangyi Lu, Yuan Wang*, Yize Wang and Xing Zhang*, “Insights into the power-off and power-on transient performance of power-rail ESD clamp circuits,” IEEE Trans. Device Mater. Rel., vol. 17, no. 3, pp. 577-584, Sep. 2017.

7. Guangyi Lu, Yuan Wang*, Lizhong Zhang, Jian Cao and Xing Zhang, “Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process,” Science China Information Sciences, vol. 59, no. 12, pp. 1–9, Dec. 2016.

8. Guangyi Lu, Yuan Wang*, Lizhong Zhang, Jian Cao, Song Jia and Xing Zhang “Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling,” Science China Information Sciences, vol. 58, no. 4, pp. 1–9, Apr. 2015.

9. Guangyi Lu, Yuan Wang*, Lizhong Zhang, Yize Wang, Ru Huang and Xing Zhang*, “Investigation on the gate bias voltage of bigFET in power-rail ESD clamp circuit for enhanced transient noise immunity,” in Proc. IEEE Int. Symp. Circuits and Systems, 2018, pp. 1-5.

10. Guangyi Lu, Yuan Wang*, Yize Wang and Xing Zhang, “Power-rail ESD Clamp Circuit with Hybrid-detection Enhanced Triggering in a 65-nm, 1.2-V CMOS Process,” in Proc. IEEE Int. Symp. Circuits and Systems, 2017, pp. 589-592.

11. Guangyi Lu, Yuan Wang*, Jian Cao, Song Jia and Xing Zhang, “A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications,” in Proc. IEEE Int. Symp. Circuits and Systems, 2016, pp. 265-268.

12. Guangyi Lu, Yuan Wang*, Yize Wang, Jian Cao and Xing Zhang, “Novel insights into the power-off and power-on transient performance of power-rail ESD clamp circuit” in Proc. EOS/ESD Symp., 2016, pp. 1-7.

13. Guangyi Lu, Yuan Wang*, Jian Cao, Qi Liu, and Xing Zhang, “Design and Verification of a Novel Multi-RC-triggered Power Clamp Circuit for On-chip ESD Protection” in Proc. EOS/ESD Symp., 2013, pp. 1-7.

欢迎具备扎实半导体器件物理、集成电路设计、机器学习算法背景的同学加入研究团队！